As semiconductor devices have become highly integrated, the size of a memory cell has been scaled down. Therefore, it is necessary to minimize the size of an isolation area. However, since the size of the isolation area is restricted due to a process of forming the isolation area and the arrangement of structures in a memory array, there are limitations in the reduction of the size of the isolation area. Accordingly, the isolation layer has been formed through a shallow trench isolation (STI) process providing a superior isolation characteristic with a narrow width instead of a local oxidation of silicon (LOCOS) process having a problem such as birds beak. In the STI process, a chemical mechanical polishing (CMP) may be performed after forming a trench in a semiconductor substrate and filling the trench with an oxide layer. However, when the isolation layer is formed through the STI process, an electric field may be concentrated on the edge of the isolation layer, so that an undesirable transistor is formed to exert an influence on the characteristic of a device.